This application is based upon and claims the benefit of priority from the prior Japanese Patent Application No. 11-342358, filed Dec. 1, 1999, the entire contents of which are incorporated herein by reference.
The present invention relates to nonvolatile semiconductor memory devices, and more particularly to a high density and high integration type nonvolatile semiconductor memory device having an improved memory cell structure.
Electrically data rewritable nonvolatile memory devices are widely used in high-speed ROMs and for mass storage devices. MOSFET type memory devices are generally used each of which has a stack gate structure comprising a charge accumulation layer or a floating gate and a control gate.
FIGS. 11A through 11C are views showing an example of a memory cell having the stack gate structure. FIG. 11A is a plan view thereof, FIG. 11B is a sectional view taken along the line bxe2x80x94b of FIG. 11A, and FIG. 11C is a sectional view taken along the line cxe2x80x94c of FIG. 11A.
In FIGS. 11A through 11C, for example, a trench for a device isolation is formed in a p-well layer 70 formed on an n-type silicon substrate. Inside of this trench, an insulation material for the device isolation, for example, a silicon dioxide is buried to form a plurality of device isolation regions 71, thereby defining device forming regions 76 between the device isolation regions 71.
On an overall surface of a channel region or the device forming region 76 which is device-isolated in such a manner, a thin tunnel insulation film 72 is formed which allows a tunnel current to flow. On the thin tunnel insulation film 72, a charge accumulation layer 73 is formed. Then, on the charge accumulation layer 73, a control gate 75 is further formed via an insulation film 74 which functions as an inter-gate insulation layer. The control gate 75 and the charge accumulation layer 73 are vertically processed in a self-aligning manner so that the side end portions are aligned as shown in FIG. 11C on a cross section in a direction of so-called word lines, namely, a direction in which the control gate 75 is extended. Furthermore, an n-type diffusion layer 77 is formed in a self-aligning manner in the device forming region 76 on both sides of each gate with respect to this side end portion. This n-type diffusion layer 77 is extended and formed between adjacent control gates 75. In this manner, a nonvolatile memory cell is formed on each part of the gate portion.
On the other hand, on the cross section of FIG. 11B in the so-called bit line direction for supplying a potential to the diffusion layer 77 of the memory cell, the charge accumulation layer 73 is cut with the insulation film 74 on the device isolation region 71 so that the charge accumulation layer 73 is divided for each of the memory cells. Then the divided charge accumulation layer 73 is capacity-coupled with the control gate 75 via the insulation film 74 between gates 73 and 75.
A data rewriting method in the nonvolatile memory cell having the above structure comprises the steps of applying a high voltage across the p-well layer 70 and the charge accumulation layer 73 to allow a tunnel current to flow through the tunnel insulation film 72 thereby exchanging the electric charge between the charge accumulation layer 73 and the p-well layer 70, thereby modulating a quantity of the electric charge in the charge accumulation layer 73 in accordance with data being written.
A channel generation threshold voltage of a memory cell becomes higher with an increase in a negative electric charge in the charge accumulation layer 73 while the threshold voltage thereof becomes lower with an increase in a positive electric charge. Consequently, when electrons are tunnel-injected into the charge accumulation layer 73, the threshold voltage is heightened with the result that the charge accumulation layer 73 is set to, for example, a datawritten state. When electrons are pulled out from the charge accumulation layer 73, the threshold voltage becomes lower so that the charge accumulation layer 73 is set to, for example, an erased state.
FIG. 12 is a view showing one example of a nonvolatile semiconductor memory device using the memory cells. In FIG. 12, there is shown a case in which the memory cells are laid out in a NAND structure. A plurality of device forming regions 76 which are isolated in a plurality of device isolation regions 71 are extended and arranged in a direction of bit lines with the result that that a plurality of control gates 75-1 to 75-n are extended and arranged in a direction which runs at right angle with the device forming region 76. A plurality of memory cells are formed in a matrix-like configuration at each of the crossing points of the control gates 75-1 to 75-n and the device forming region 71, and n-type diffusion layers 77 are formed in the device forming region 76 between the respective control gates 75-1 to 75-n.
As a consequence, a plurality of memory cells are connected in series in a direction of bit lines via the n-type diffusion layers 77 to constitute a unit block. Each of the unit blocks is connected to the bit line contact 81 via the selection gate 80 formed of a transistor. Outside of the selection gates 82 on the opposite side of the bit line contacts 81 in the unit blocks a common source line 83 is arranged and is connected via the n-type diffusion layer 77. Incidentally, the bit line contacts 81 are connected to bit line signal lines not shown.
Along with an increase in the memory capacity of the nonvolatile semiconductor memory device, an increase in the density of the memory cell is extremely important, and a shrinkage in the memory size through the refinement of the memory cell is effective means for the realization of the increase in the density of the memory device. For this purpose, it is most important to suppress the disparity in the size of each of the memory devices in addition to the refinement of the stack gate and the device forming region or the like.
With respect to the stack gate structure, as explained in FIG. 11C, it is effective to align the side walls or side end portion in a self-aligning manner by processing collectively the second gate insulation film 74 and the charge accumulation layer 73 at the time of processing the control gate 75.
On the other hand, with respect to the width of the device forming region or the width of the device isolation region, it is important to set the width of the charge accumulation layer 73 and the width of the device forming region to an equal size. There is proposed a self-aligning method for forming a charge accumulation layer in advance followed by forming in a self-aligning manner a device forming region in alignment with the charge accumulation layer (Japanese Patent Application No. 6-150241).
FIGS. 13A through 13C are views showing one example of a memory cell having a self-aligning type device isolation structure. FIG. 13A is a plan view, FIG. 13B is a sectional view taken along the line bxe2x80x94b of FIG. 13A, and FIG. 13C is a sectional view taken along the line cxe2x80x94c of FIG. 13A in the same manner.
For example, as shown in FIG. 13B, a trench for the device isolation is formed inside of the p-well layer 90. Inside of the trench, an insulation material for the device isolation, for example, silicon dioxide is buried, so that a device isolation region 91 is formed. On the overall surface of the channel region on the p-well layer 90 which is device-isolated, a thin tunnel insulation film 92 is formed which allows a tunnel current to flow.
On the tunnel insulation film 92, as shown in FIGS. 13A and 13C, a conductive layer 93a which forms a part of the charge accumulation layer 93 and which has a side end portion aligned with the device forming region 96 is formed. On the conductive layer 93a, another conductive layer 93b is formed, so that the conductive layer 93a and the conductive layer 93b are electrically set to the same potential and a laminated layer type charge accumulation layer 93 is formed. On the laminated type charge accumulation layer 93, a control gate 95 is formed via an insulation film 94 functioning as an inter-gate insulation film.
The control gate 95 and the laminated type charge accumulation layer 93 are vertically processed in a self-aligning manner so that the side end portions are aligned as shown in FIG. 13C in a so-called word line direction cross section on which the control gate 95 is extended with the result that the n-type diffusion layer 97 is formed between the gates.
On the other hand, on the so-called bit line direction cross section on which a potential is supplied to the diffusion layer 97 of the memory cell, as shown in FIG. 13B, the conductive layer 93b is cut with the insulation film 94 between the gates on the device isolation region 91 and the conductive layer 93b is cut for each of the memory cells with the result that the charge accumulation layer 93 is electrically separated for each of the memory cells. The charge accumulation layer 93 is capacity-coupled with the control gate 95 via the insulation film 94 between the gates.
FIGS. 14B1 through 14B5, and 14C1 through 14C5 are explanatory views showing a procedure of steps for manufacturing a memory cell having a structure shown in FIGS. 13A through 13C. FIGS. (14B1 through 14B5) on the left row of the drawings are sectional views taken along the line bxe2x80x94b of FIG. 13A while figures (14C1 through 14C5) on the right row are sectional views taken along the line cxe2x80x94c of FIG. 13A.
As shown in FIGS. 14B1 and 14C, a first conductive layer 93a is formed via the first gate insulation film 92 which forms a tunnel oxide film on, for example, the p-well 90, thereby forming a mask material 101 which forms a processed mask of the conductive layer 93a. 
Next, as shown in FIGS. 14B2 and 14C2, the mask material 101 and the conductive layer 93a are patterned by using the lithography technique so that the mask material 101 and the conductive layer 93a are retained on the device forming region 96 thereby removing the mask material 101 and the conductive layer on the region where the device isolation region 91 is to be formed. Consequently, the first gate insulation film 92 and p-well 90 are removed by dry etching by using the retained mask material 101 thereby forming a trench 102.
At this time, the trench 102 and the side walls of the first conductive layer 93a are aligned. Furthermore, the depth of the trench 102 can be selected in accordance with the desired device isolation endurance pressure.
Next, after cleaning or an appropriate surface treatment is conducted, as shown in FIGS. 14B3 and 13C3, the insulation film 91 for the device isolation is buried in the trench 102, so that the buried film 91 is planarized and the thickness of the film is adjusted by polishing or etch-back. Thus, the device isolation region 91 is completed.
Next, as shown in FIGS. 14B4 and 14C4, after the mask material 101 is removed, a second conductive film 93b is directly formed on the conductive layer 83b. As shown in FIG. 14B4, the conductive layer 93b is cut with the slit 103 on the device isolation region 91, so that the charge accumulation layer 93 is isolated for each of the memory cells.
Lastly, as shown in FIGS. 14B5 and 14C5, after the second gate insulation film 94 and a conductive layer which forms the control gate 95 are formed, the control gate 95, the second gate insulation film 94, and the charge accumulation layer 93 are processed collectively in a direction of intersecting the device forming region 96 by dry etching. Consequently, as shown in FIG. 14C5, the side end portions of the members 93, 94 and 95 are aligned.
In the case where such a self-aligning type device isolation structure is formed, there is a problem in that the characteristic of the buried structure becomes wrong because the aspect ratio which is a ratio of the thickness and the width of the insulation film 91 at the time of burying the insulation film 91 for the device isolation in the trench 102 becomes large by the increase of the thickness of the first conductive layer 93a. Specifically, voids are generated inside of the buried device isolation insulation film 91 so that the voids are exposed on the surface at the time of the later planarization and the planarity is lost.
Furthermore, there is a problem that the residual of the gate material is generated at the time of processing the gate, so that a short-circuiting occurs between the charge accumulation layers 93 between the adjacent memory cells.
Such problem becomes more serious with an increase in the aspect ratio as described above. In the case where the width of the device isolation is narrowed along with the refinement of the device, the pitch of the bit line is narrowed and the width of the device forming region is narrowed in an effective manner, and in the case where the trench is deep, the problem becomes more conspicuous.
For example, when the width of the device isolation is 0.25 xcexcm or less, and the depth of the trench is 0.25 xcexcm or more, the problem is especially serious.
On the other hand, the residual of the conductive layer 93 between adjacent gates 95 must be completely removed at the time of processing the gate in FIGS. 14B5 and 14C5. However, when the pitch of the word line is narrowed along with the refinement, the gate width and the gate interval are narrowed so that the etching rate of the dry etching is lowered. In the case where the gate width and the gate interval have a wide and narrow portions in a mixed manner, the material for the charge accumulation layer 93 of an array portion such as a memory cell or the like are not removed and retained as residuals when etching is conducted in alignment with the wide region, so that a short-circuiting failure occurs between adjacent memory cells. The above problem becomes particularly conspicuous when the memory cells are formed with the gate width and the gate interval of 0.2 xcexcm or less.
As described above, in the case where the self-alignment device isolation method is used in an attempt to increase the capacity and the density of the nonvolatile semiconductor memory device, the possibility becomes large that a problem arises such that the burring performance of the insulation film for the device isolation into the trench is abruptly deteriorated and the removal characteristic of the charge accumulation layer on the side end of the device isolation region is also abruptly deteriorated when the refinement size of the cell exceeds a certain value.
The above problem is likely to arise in all the nonvolatile semiconductor memory devices having a device isolation structure formed with the self-aligning method in the cell array structure other than the NOR type, the AND type, and NAND type including the DINOR type.
As has been described above, in the case where the self-alignment type isolation method is used in an attempt to increase the capacity and the density of the nonvolatile semiconductor memory device, there is a possibility that a problem arises such that the burying performance of the insulation film for the device isolation into the trench is abruptly deteriorated and the removal characteristic of the charge accumulation layer on the side end of the device isolation region is also abruptly deteriorated along with the refinement of the memory cells.
The present invention has been made in view of the above circumstances, and an object of the present invention is to provide, by solving the above problem, a large capacity, high density and low cost nonvolatile semiconductor memory device which can be constituted so that no residual is generated on both side end of the device isolation region at the time of gate processing while improving the buried characteristic of the device isolation region by forming the conductive layer which is a part of the charge accumulation layer with a tapered angle of 80 degrees or more and less than 90 degrees.
In order to solve the above problem, the present invention provides a nonvolatile semiconductor memory device in which a plurality of memory cells are arranged in an array-like configuration to constitute a cell array having a plurality of device isolation regions buried by an insulation material in trenches formed in a semiconductor substrate, and a plurality of device forming regions each of which is divided with the device isolation regions, and in which each of the memory cells includes a charge accumulation layer formed via a first gate insulation film on the device forming region, and a control gate formed on the charge accumulation layer via a second gate insulation film,
wherein at least a portion of the charge accumulation layer sandwiched with the device isolation regions has a lower end with a width larger than that of an upper end of the sandwiched portion, and the device isolation regions each has a width of 0.25 xcexcm or less.
The charge accumulation layer is such that the buried configuration of the device isolation region is improved by narrowing the width of the upper end of the charge accumulation layer than the width of the lower end thereof at least at the portion sandwiched with the device isolation regions thereby enabling to set the width of the device isolation to be 0.25 xcexcm or less.
Additional objects and advantages of the invention will be set forth in the description which follows, and in part will be obvious from the description, or may be learned by practice of the invention. The objects and advantages of the invention may be realized and obtained by means of the instrumentalities and combinations particularly pointed out hereinafter.